1. Field of the Invention
The present invention relates to a packet buffer for temporarily storing reception packets and sending out those according to predetermined rules in an apparatus such as a router or a switch that performs packet switching. In particular, the invention relates to a technique of performing control so that transfer order of packets is determined by applying to the packets priority order that is different from their arrival order, in accordance with transfer quality required for each packet.
2. Description of the Related Art
With rapid spread of the Internet, data communication services using the Internet have advanced by leaps and bounds. The traffic of data communication using packets as typified by IP (Internet protocol) packets are now coming to occupy the main part of that of the entire data communication. There has been increasing demand for the data communication services using the Internet, especially for transmission of voice data or video data or the like in which real-time operation is essential.
In the above circumstances, also demanded are techniques so-called QoS (quality of service) which realize transmission of video data, voice data, or the like that is encapsulated in IP packets while keeping high quality. As QoS for routers and switches, a control technique for sending reception packets in a different order from their arrival order in accordance with data transfer quality that is set for each packet is needed.
In general, in an apparatus such as a router or a switch that performs packet switching, a packet buffer is located upstream of a hardware switch or the like for selecting an outgoing transmission path and has a role of temporarily storing reception packets and sending out the stored packets according to predetermined rules.
FIG. 13 shows the configuration of a first conventional packet buffer.
In the packet buffer of FIG. 13, a classifying section 411 extracts information relating to a service class from a reception packet, communicates this information to a scheduler 412, and passes the reception packet to a write controlling section 413. If necessary, the scheduler 412 divides a reception packet into units of write to a common buffer 414 and inputs a write request for each write unit to the write controlling section 413. At this time, the scheduler 412 assigns an address management list to each reception packet. Each list has chain information on a plurality of write units formed by dividing the associated reception packet as well as write address of the respective write units. Further, the scheduler 412 adjusts the read order of reception packets stored in the common buffer 414 based on the pieces of information relating to service classes that have been communicated from the classifying section 411, and inputs read requests for the respective reception packets to a read controlling section 415 according to the read order thus determined. At this time, the scheduler 412 informs the read controlling section 415 about the lists corresponding to the respective packets. In response, the read controlling section 415 sequentially reads data of each packet based on addresses shown in each specified list from the common buffer 414.
As described above, in the packet buffer of FIG. 13, a transmission control suited for service classes is realized in such a manner that arrival packets are stored in the common buffer 414 and the packets are read from the common buffer 414 according to a read order determined by the scheduler 412 based on the service classes.
FIG. 14 shows the configuration of a second conventional packet buffer.
The packet buffer of FIG. 14 has FIFOs 421 corresponding to respective service classes. In this packet buffer, the classifying section 422 sends a reception packet to an FIFO 421 that is suitable for its service class and communicates, to a scheduler 423, information indicating the FIFO 421 to which the reception packet is sent. The scheduler 423 schedules read operations according to the FIFOs 421 based on priority ranks that are set for the respective FIFOs 421, and informs a buffer selecting section 424 of the FIFO 421 to be selected.
As described above, in the packet buffer of FIG. 14, a transmission control based on service classes is realized in such a manner that arrival packets are stored in the FIFO 421 having a suitable service class and the buffer selecting section 424 sequentially sends packets stored in the FIFO 421 that is specified by an instruction from the scheduler 423.
In the packet buffer of FIG. 13, since packets are read from the common buffer 414 according to priority order that is irrelevant to order of arrival, random read addresses are inputted to the common buffer 414. Write addresses are determined also randomly because reception packets are written to the common buffer 414 while free areas that occur randomly on the common buffer 414 are managed by using a list as reception packets are read out randomly.
Therefore, to realize a high-speed router using the packet buffer of FIG. 13 to accommodate increase in data communication rate, naturally a memory device exhibiting high-speed random access performance in both reading and writing is necessary as the common buffer 414. That is, the price of the router depends on the price of the memory device used as the common buffer 414 and the performance of the router is determined by the performance of the memory device.
On the other hand, in the packet buffer of FIG. 14, the FIFO 421 needs to be provided for the respective service classes though the packet arrival frequencies of the respective service classes have large variations. Therefore, the memory use efficiency becomes very low in the FIFOs 421 provided for service classes having low packet arrival frequencies. Further, for adjusting reads and writes, another buffer separate from the FIFOs 421 for the respective service classes is necessary. As a result, a processing cycle that can be attained by the packet buffer of FIG. 14 is longer than a value corresponding to a maximum packet arrival frequency.
As described above, whichever conventional packet buffer is employed, a high cost is needed to realize a high transmission capability.